Email ID : suchithranp.ait@gmail.com suchithra.mtech@gmail.com

Vidwan ID : https://vidwan.inflibnet.ac.in/profile/725653

Google Scholar ID : http://scholar.google.com/citations?hl=en&user=SZJzs50AAAAJ

Orcid ID : https://orcid.org/0009-0006-2273-6600

LinkedIn ID : https://www.linkedin.com/in/suchithra-n-p-609ab9211/

Program: Electronics and Communication Engineering

Teaching:  12 Years

Research: 3

Industry: 1

 

ACADEMIC DETAILS

• Pursuing PhD in Image Processing

• M.Tech in Digital Electronics

• BE in Electronics and Communication Engineering

 

AREAS OF INTEREST

• VLSI in both front end and back end, Image Processing

 

PUBLICATION DETAILS

 

International Journal:

1. Suchithra N P, Naveen Kumar M, Jayashree C Nidagundi “Low Power and High-Speed Clock Triggered Comparator Using 0.18µm Technology”, CIIT International Journal of Programmable Device Circuits and Systems, Coimbatore, ISSN 0974 -973X, Volume 3, No. 8, pp 436 to 440, July 2011.

2.  Khushi K, Manu B M, Pallavi B H, Pushpa R K, Mrs. Suchitra N P “Enhanced Protection Methods for Women’s Safety Using IOT” IJIRT International Journal of Innovative Research in Technology ISSN-2349-6002

3.  Suchithra N P and Viswanath K, "Development of HAR using Spatio Temporal Machine Learning Techniques," GRENZE International Journal of Engineering and Technology, vol. 12, no. 2, 2026.

4.  Suchithra N P, Dr. K. Viswanath, “Review on Human Movement Analysis, Gesture Recognition, and Emotion Detection using Computational and Sensor-Based Approaches", International Journal of Creative Research Thoughts (IJCRT), ISSN:2320-2882, Volume.14, Issue 6, pp. d377-d387, June 2026.

 

International Conference:

1. Suchithra N P, Naveen Kumar M, Jayashree C Nidagundi “Low Power Asynchronous Binary-Search ADC Using Clock Gating Technique”, International Conference ICFOCS 2011, JN Tata Convention Center, IISc, Bangalore, ISBN-978-81-921929-0-1-, 7 -9 August 2011.

 

National Conference:

1. Suchithra N P, Naveen Kumar M, Jayashree C Nidagundi “Design and Implementation of 3-bit Asynchronous Binary-Search ADC Architecture”, National Conference NCSCV’11, Dept. of E&CE, Anna University of Technology, Coimbatore, 6-7 May 2011, pp 56 to 61.

2.  Suchithra N P, Naveen Kumar M, Jayashree C Nidagundi “Design and Simulation of Low Power and High-Speed Comparator using VLSI Technology”, National Conference NCSCV’11, Dept. of E&CE, Anna University of Technology, Coimbatore, 6-7 May 2011, pp 372 to 376.

3.  Suchithra N P, Naveen Kumar M, Jayashree C Nidagundi “3-bit Asynchronous Binary-Search ADC Architecture using 0.18µm Technology” in the national conference, CETIT-2011 organized by Department of PG Studies, Visvesvaraya Technological University, Belgaum held on 20-22 May 2011.

4.  Adithya, Suchithra N P “Aid for the Blind’s using Raspberry Pi” on 22nd July 2022 National Conference on Advanced and Recent Trends in Electronics & Communication NCAREC-22 organized by Dept. of ECE SKIT Bangalore.

5.  Suchithra N P, Rakshitha R, Shamitha Pujari “Realization of Cryptography algorithm for Secure Communication” at the National Conference on Advances in Science, Engineering & Technology NCASET2025 organized by the Dept. of ECE Dr. SMCE.

 

FDPS/CONFERENCES/WORKSHOPS/STTP/MOOC CERTIFICATION

 

Certificate Course:

• Successfully completed training program “Design Verification”, conducted during October 08, 2022 to February 20, 2023 at Chip Edge Technologies Pvt. Ltd., Bangalore.

 

FDP Attended:

• Attended National Level Faculty Development programme on “Augmented Reality, Virtual Reality and Internet of Things” held from 20th to 24th August 2024 0rganized by Akshaya Institute of Technology Tumkur.

• Attended FDP on “Semiconductor Fabrication & Packaging Technology” from 20th to 31st January 2025 organized by EICT Academy, IIT Roorkee from 20th to 31st January 2025.

• Attended FDP on “Trends and Challenges in Semiconductor Technology, Artificial Intelligence and Machine Learning: Research Perspective”, sponsored by Ministry of Electronics Information Technology (Meity) government of India E and ICT Academy NIT Warangal association with JSS Academy Bengaluru from 23rd June - 2nd July 2025.  

• Attended FDP on “AI for Educators” in November 2025 organized by SKIT Bangalore.

• Attended IEP on “ASIC Design Flow using SCL 180nm Technology” during the period 23rd Feb to 27th Feb 2026 organized by Cambridge Institute of Technology Bangalore.

 

Workshop Conducted:

• Three Days Workshop on Chipcraft: “VLSI Design Training using Cadence EDA” at Akshaya Institute of Technology, Tumakuru.

 

Technical Talk Delivered:

• Delivered technical talk on “FPGA Based Digital System Design”, at Acharya Institute of Technology, Bangalore.

• Delivered technical talk on “Emerging application on recent FPGA Architectures” at Akshaya Institute of Technology, Tumakuru.

 

Designed and conducted skill lab programme on:

• RTL based Digital System Design using Verilog.

• FPGA based System Design using Verilog.

• Kick Starts on Digital VLSI using Cadence Tool.

• Design and Implementation of Industry Standard Communication Protocol using Synopsis Tool.

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